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Chapter 3: Design Rules and Procedures
Frequency Design Rules
Two DSP Builder blocks can operate with two different sampling periods.
However for most DSP Builder blocks, the sampling period of each input port and
each output port must be identical.
Although this rule applies most of the DSP Builder blocks, there are some
exceptions such as the Dual-Clock FIFO block where the sampling period of the
read input port is expected to be different than the sampling period of the write
input port.
For a datapath using mixed clock domains, the design may require additional
register decoupling around the register that is between the domains.
This requirement is especially true when the source data rate is higher than the
destination register, in other words, when the data of a register is toggling at the
higher rate than the register ’s clock pin ( Figure 3–9 ).
Figure 3–9. Data Toggling Faster than Clock
Figure 3–10 shows a stable hardware implementation.
Figure 3–10. Stable Hardware Implementation
Using Clock and Clock_Derived Blocks
DSP Builder maps the Clock and Clock_Derived blocks to two hardware device input
pins; one for the clock input, and one for the reset input for the clock domain. A
design may contain zero or one Clock block and zero or more Clock_Derived blocks.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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